IBM has unveiled the prototype of a chip capable of reducing power consumption by up to 85%, with a design that allows transistors to be stacked vertically on the surface of the chip.
Developed in partnership with Samsung Electronics in Albany, NY, IBM’s Nanotech Center, IBM plans to use the processor not only in its server-based systems, where it can reduce power requirements for cryptomining operations and tasks of data encryption, but in a range of consumer devices, including cell phones that can hold a charge for up to a week.
For example, IBM believes there is a significant opportunity for new chips among IoT and edge devices where its power saving properties could come in handy as power sources are not available, such as buoys. oceanic, autonomous vehicles and spacecraft.
An analyst said he believes the upcoming technology holds promise for users to improve their mobile and advanced technologies by building more reliable systems and devices.
“As cutting-edge strategies begin to take hold, the way we connect and stay connected for significant periods of time or improve the computing power of remote systems for AI grows in importance,” said Dan Newman , founding partner and principal analyst of Futurum Research. “Announcements like this from IBM or Arm looking to solve tough problems like this are a big development. “
Advantages of vertical stacking of processor transistors
The ability to stack transistors vertically instead of laying them flat on the chip surface not only allows vendors to pack many more transistors on a chip, but is also the primary reason for the upcoming design of the chip is much more energy efficient.
Chipmakers and business users alike can benefit from the new design as it allows them to bypass the constraints of Moore’s Law, the principle established by Gordon Moore of Intel in 1965 that there would be a doubling of the number. of transistors on an electronic chip every two years, then overhauled every 18 months. But in recent years, chipmakers have started to run out of “real estate” on processors to insert other transistors.
The new technology centers on IBM’s vertical transport field effect transistors (VTFETs) to implement transistors perpendicular to the chip surface, allowing upward and downward flow of electric current. This allows for greater current flow and eliminates wasted energy, IBM said.
The new chip represents IBM’s attempts to “defy convention and rethink how the chip industry can improve business and reduce environmental impact,” said Mukesh Khare, vice president of hybrid cloud and systems at IBM Research, in a press release.
IBM will have some formidable competitors in this market, as Intel and Taiwan Semiconductor Manufacturing Company (TSCM) plan to launch new chip designs during the period 2023-2024.
Earlier this month, Intel said it is investing significant research in scaling technologies to deliver more transistors, but is taking a different approach than IBM. Company researchers described solutions to the design, process and assembly challenges of the hybrid link interconnect. They believe this approach will result in more than a ten-fold improvement in interconnect density in terms of packaging.
At its fast-track conference in July, Intel announced plans to introduce Foveros Direct, allowing bump pitches of less than 10 microns. This capacity would allow an increase of an order of magnitude in the interconnection density for the 3D stack. This in turn allows the ecosystem to take advantage of advanced packaging.
IBM, meanwhile, believes its redesign can help processor developers create a new device architecture that would speed up the scaling of semiconductor devices beyond the nanosheet.
Frank DzubeckPresident, Communications Network Architects, Inc.
The next chips, which should be available sometime in 2024, will be used in future IBM Power servers as well as their Z series of mainframes. Samsung also makes the seven-nanometer chips for IBM’s Power 10 servers as well as the IBM Telum processor unveiled earlier this year, both of which are based on IBM designs.
“IBM can take this technology in many directions,” said Frank Dzubeck, president of Communications Network Architects, Inc. “They can extend it for internal use with their Power series and mainframes, but also allow it externally. to a variety of companies working in both high tech and consumer markets. “
The new technology is also benefiting IBM’s manufacturing processes for future two-nanometer, one-nanometer and sub-nanometer chips, which could keep them competitive over the next several years with Intel, Arm and TSCM.
“This new technology looks like a modification of the same technology IBM will use to produce nanometer chips, except you can stack [transistors] vertically, “Dzubeck said.” And with this level of energy savings, their water-cooled mainframe computers may not need water, which keeps costs down. “
As Editor-in-Chief in TechTarget’s News Group, Ed Scannell is responsible for writing and reporting the latest news, news analysis and features focused on technology issues and trends affecting business professionals. IT in business. He also worked for 26 years at Infoworld and Computerworld covering the enterprise-class products and technologies of major IT companies, notably IBM and Microsoft, and was editor-in-chief of Redmond for three years, overseeing the editorial content of this magazine.